<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3247384</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Wed Nov  3 18:03:37 2021</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2021.1 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>57e6ddbdc10642c7af5f35e42ed68b39</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>5</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>9a2b349767e754759f222c5a7e18f498</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>9a2b349767e754759f222c5a7e18f498</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a200t</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>fbg676</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-2</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>AMD Ryzen 7 4800H with Radeon Graphics         </TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2895 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>16.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>abstractcombinedpanel_move_selected_element_up=1</TD>
   <TD>abstractcombinedpanel_remove_selected_elements=3</TD>
   <TD>abstractfileview_reload=5</TD>
   <TD>abstractselectabletablepanel_export_to_spreadsheet=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>addsrcwizard_specify_hdl_netlist_block_design=10</TD>
   <TD>addsrcwizard_specify_or_create_constraint_files=4</TD>
   <TD>addsrcwizard_specify_simulation_specific_hdl_files=3</TD>
   <TD>basedialog_apply=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_cancel=49</TD>
   <TD>basedialog_no=1</TD>
   <TD>basedialog_ok=382</TD>
   <TD>basedialog_yes=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>basereporttab_rerun=1</TD>
   <TD>boardchooser_board_table=2</TD>
   <TD>checktimingsectionpanel_check_timing_selection_table=13</TD>
   <TD>closeplanner_yes=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>cmdmsgdialog_messages=13</TD>
   <TD>cmdmsgdialog_ok=30</TD>
   <TD>cmdmsgdialog_open_messages_view=13</TD>
   <TD>commandsinput_type_tcl_command_here=28</TD>
</TR><TR ALIGN='LEFT'>   <TD>constraintschooserpanel_add_existing_or_create_new_constraints=1</TD>
   <TD>constraintschooserpanel_add_files=5</TD>
   <TD>constraintschooserpanel_add_files_below_to_this_constraint_set=2</TD>
   <TD>constraintschooserpanel_create_file=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>constraintschooserpanel_file_table=9</TD>
   <TD>createconstraintsfilepanel_file_location=5</TD>
   <TD>createconstraintsfilepanel_file_name=6</TD>
   <TD>createnewdiagramdialog_design_name=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>createnewdiagramdialog_directory=2</TD>
   <TD>createsrcfiledialog_file_location=1</TD>
   <TD>createsrcfiledialog_file_name=2</TD>
   <TD>createsrcfiledialog_file_type=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>deviceconstraintsview_internal_vref_tree=2</TD>
   <TD>editcreateclocktablepanel_edit_create_clock_table=1</TD>
   <TD>editiodelaytablepanel_edit_io_delay_table=8</TD>
   <TD>exploreaheadview_launch_selected_runs=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>exportportsdialog_export_io_ports=2</TD>
   <TD>exporttospreadsheetdialog_choose_microsoft_excel_file_to_export=3</TD>
   <TD>expreporttreepanel_exp_report_tree_table=21</TD>
   <TD>exprunmenu_change_run_settings=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>exprunmenu_launch_runs=1</TD>
   <TD>exprunmenu_launch_step=1</TD>
   <TD>exprunproppanels_constraints=1</TD>
   <TD>expruntreepanel_exp_run_tree_table=46</TD>
</TR><TR ALIGN='LEFT'>   <TD>filesetpanel_file_set_panel_tree=1059</TD>
   <TD>floorplaneditor_metric=1</TD>
   <TD>flownavigatortreepanel_flow_navigator_tree=283</TD>
   <TD>fpgachooser_family=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>fpgachooser_fpga_table=15</TD>
   <TD>fpgachooser_package=1</TD>
   <TD>getobjectsdialog_find=1</TD>
   <TD>gettingstartedview_create_new_project=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>gettingstartedview_open_project=9</TD>
   <TD>graphicalview_zoom_fit=142</TD>
   <TD>graphicalview_zoom_in=18</TD>
   <TD>graphicalview_zoom_out=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>hardwaresiolinksview_create=1</TD>
   <TD>hardwaretreepanel_hardware_tree_table=67</TD>
   <TD>hcodeeditor_blank_operations=2</TD>
   <TD>hcodeeditor_commands_to_fold_text=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>hcodeeditor_diff_with=2</TD>
   <TD>hfiltertoolbar_hide_all=1</TD>
   <TD>hfiltertoolbar_show_all=1</TD>
   <TD>hinputhandler_reformat_code=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>hpopuptitle_close=1</TD>
   <TD>htable_set_eliding_for_table_cells=1</TD>
   <TD>instanceproppanels_reference_name=1</TD>
   <TD>instanceproppanels_type=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>iodelaycreationpanel_delay_value=2</TD>
   <TD>iodelaycreationpanel_specify_clock_pin_or_port=1</TD>
   <TD>iodelaycreationpanel_specify_list_of_ports=1</TD>
   <TD>labtoolsmenu_jtag_scan_rate=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>logmonitor_monitor=43</TD>
   <TD>mainmenumgr_checkpoint=2</TD>
   <TD>mainmenumgr_design_hubs=1</TD>
   <TD>mainmenumgr_edit=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_export=3</TD>
   <TD>mainmenumgr_file=16</TD>
   <TD>mainmenumgr_floorplanning=1</TD>
   <TD>mainmenumgr_flow=20</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_help=6</TD>
   <TD>mainmenumgr_io_planning=1</TD>
   <TD>mainmenumgr_ip=2</TD>
   <TD>mainmenumgr_open=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_partial_reconfiguration=1</TD>
   <TD>mainmenumgr_project=9</TD>
   <TD>mainmenumgr_reports=6</TD>
   <TD>mainmenumgr_run=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_settings=7</TD>
   <TD>mainmenumgr_text_editor=2</TD>
   <TD>mainmenumgr_tools=10</TD>
   <TD>mainmenumgr_view=12</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_window=12</TD>
   <TD>mainwinmenumgr_layout=10</TD>
   <TD>mainwintoolbarmgr_select_or_save_window_layout=12</TD>
   <TD>messagewithoptiondialog_dont_show_this_dialog_again=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>msgtreepanel_message_severity=10</TD>
   <TD>msgtreepanel_message_view_tree=1151</TD>
   <TD>msgview_warning_messages=2</TD>
   <TD>navigabletimingreporttab_timing_report_navigation_tree=152</TD>
</TR><TR ALIGN='LEFT'>   <TD>netlistschmenuandmouse_view=11</TD>
   <TD>netlisttreeview_netlist_tree=33</TD>
   <TD>netproppanels_load_direct_routing_constraint=1</TD>
   <TD>nettablepanel_net_table=12</TD>
</TR><TR ALIGN='LEFT'>   <TD>newprojectwizard_rtl_project_you_will_be_able_to_add=1</TD>
   <TD>overwriteconstraintsdialog_cancel=1</TD>
   <TD>overwriteconstraintsdialog_overwrite=2</TD>
   <TD>overwriteconstraintsdialog_save_constraints_as=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>packagetreepanel_package_tree_panel=4</TD>
   <TD>pacommandnames_add_config_memory=1</TD>
   <TD>pacommandnames_add_sources=42</TD>
   <TD>pacommandnames_auto_connect_target=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_auto_update_hier=129</TD>
   <TD>pacommandnames_bitstream_settings=3</TD>
   <TD>pacommandnames_close_target=1</TD>
   <TD>pacommandnames_create_hardware_dashboards=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_export_pinout=2</TD>
   <TD>pacommandnames_goto_implemented_design=1</TD>
   <TD>pacommandnames_goto_netlist_design=1</TD>
   <TD>pacommandnames_goto_project_manager=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_goto_source=1</TD>
   <TD>pacommandnames_log_window=2</TD>
   <TD>pacommandnames_make_active_cnsset=2</TD>
   <TD>pacommandnames_move_to_sim_set=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_new_project=3</TD>
   <TD>pacommandnames_open_hardware_manager=2</TD>
   <TD>pacommandnames_open_target=1</TD>
   <TD>pacommandnames_properties_window=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_refresh_device=1</TD>
   <TD>pacommandnames_reports_window=1</TD>
   <TD>pacommandnames_run_bitgen=6</TD>
   <TD>pacommandnames_schematic=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_set_as_top=16</TD>
   <TD>pacommandnames_set_target_ucf=6</TD>
   <TD>pacommandnames_set_used_in_prop=2</TD>
   <TD>pacommandnames_show_bus_plot=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_live_break=1</TD>
   <TD>pacommandnames_simulation_live_restart=59</TD>
   <TD>pacommandnames_simulation_live_run=103</TD>
   <TD>pacommandnames_simulation_live_run_all=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_relaunch=1</TD>
   <TD>pacommandnames_simulation_reset=44</TD>
   <TD>pacommandnames_simulation_run=72</TD>
   <TD>pacommandnames_simulation_run_behavioral=121</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_run_post_synthesis_functional=3</TD>
   <TD>pacommandnames_src_enable=3</TD>
   <TD>pacommandnames_toggle_view_nav=5</TD>
   <TD>pacommandnames_verify_device=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_view_run_log=1</TD>
   <TD>pacommandnames_zoom_fit=7</TD>
   <TD>pacommandnames_zoom_in=8</TD>
   <TD>pagraphicalview_view=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>pathmenu_set_false_path=12</TD>
   <TD>pathmenu_set_maximum_delay=10</TD>
   <TD>pathmenu_set_multicycle_path=12</TD>
   <TD>pathreporttableview_description=42</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_code=27</TD>
   <TD>paviews_device=13</TD>
   <TD>paviews_ip_catalog=2</TD>
   <TD>paviews_package=25</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_par_report=1</TD>
   <TD>paviews_project_summary=90</TD>
   <TD>paviews_schematic=10</TD>
   <TD>paviews_system=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_tcl_object_view=1</TD>
   <TD>planaheadtab_show_flow_navigator=5</TD>
   <TD>portmenu_configure_io_ports=2</TD>
   <TD>powerresultsummarypanel_thermal_margin=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>powerresulttab_report_navigation_tree=2</TD>
   <TD>programdebugtab_open_target=1</TD>
   <TD>programdebugtab_program_device=3</TD>
   <TD>programfpgadialog_program=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>progressdialog_cancel=2</TD>
   <TD>projectfilechooserpanel_new_script=1</TD>
   <TD>projectnamechooser_choose_project_location=1</TD>
   <TD>projectnamechooser_project_name=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>projectsummarypowerpanel_tabbed_pane=2</TD>
   <TD>projectsummarytimingpanel_project_summary_timing_panel_tabbed=6</TD>
   <TD>projectsummaryutilizationgadget_project_summary_utilization_gadget_tabbed=2</TD>
   <TD>projectsummaryutilizationpanel_project_summary_utilization_panel_tabbed=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>projecttab_close_design=2</TD>
   <TD>projecttab_reload=1</TD>
   <TD>propertiesview_next_object=1</TD>
   <TD>propertiesview_previous_object=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>propertypanels_statistics_table=2</TD>
   <TD>quickhelp_help=2</TD>
   <TD>rdicommands_custom_commands=1</TD>
   <TD>rdicommands_delete=33</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_properties=9</TD>
   <TD>rdicommands_settings=1</TD>
   <TD>rdicommands_undo=1</TD>
   <TD>rdicommands_waveform_save_configuration=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdiviews_waveform_viewer=1133</TD>
   <TD>reportnavigationholder_save=3</TD>
   <TD>rungadget_show_error_and_critical_warning_messages=4</TD>
   <TD>rungadget_show_warning_and_error_messages_in_messages=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>saveprojectutils_dont_save=1</TD>
   <TD>saveprojectutils_save=3</TD>
   <TD>saveschematicdialog_specify_output_pdf_file=9</TD>
   <TD>schmenuandmouse_save_as_pdf_file=11</TD>
</TR><TR ALIGN='LEFT'>   <TD>selectmenu_highlight=16</TD>
   <TD>selectmenu_mark=16</TD>
   <TD>settingsdialog_options_tree=4</TD>
   <TD>settingsdialog_project_tree=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>settingsprojectgeneralpage_choose_device_for_your_project=5</TD>
   <TD>signaltreepanel_signal_tree_table=387</TD>
   <TD>simulationforcesettingsdialog_force_value=11</TD>
   <TD>simulationforcesettingsdialog_value_radix=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationliverunforcomp_specify_time_and_units=12</TD>
   <TD>simulationobjectspanel_simulation_objects_tree_table=3</TD>
   <TD>simulationscopespanel_simulate_scope_table=238</TD>
   <TD>srcchooserpanel_add_directories=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcchooserpanel_add_files_below_to_this_simulation_set=9</TD>
   <TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=37</TD>
   <TD>srcchooserpanel_add_sources_from_subdirectories=6</TD>
   <TD>srcchooserpanel_create_file=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcchooserpanel_make_local_copy_of_these_files_into=6</TD>
   <TD>srcchoosertable_src_chooser_table=43</TD>
   <TD>srcmenu_ip_hierarchy=131</TD>
   <TD>srcmenu_refresh_hierarchy=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcmenu_set_file_type=1</TD>
   <TD>srcmenu_set_library=1</TD>
   <TD>stalerundialog_no=2</TD>
   <TD>stalerundialog_yes=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>systembuilderview_add_ip=1</TD>
   <TD>systemtreeview_system_tree=3</TD>
   <TD>taskbanner_close=138</TD>
   <TD>tclconsoleview_tcl_console_code_editor=86</TD>
</TR><TR ALIGN='LEFT'>   <TD>tclobjecttreetable_treetable=51</TD>
   <TD>timingdialogutils_results_name=9</TD>
   <TD>timingitemflattablepanel_floorplanning=3</TD>
   <TD>timingitemflattablepanel_table=42</TD>
</TR><TR ALIGN='LEFT'>   <TD>timingitemflattablepanel_view_path_report=1</TD>
   <TD>timingsumresultstab_report_timing=1</TD>
   <TD>viotreetablepanel_vio_tree_table=4</TD>
   <TD>waveformnametree_waveform_name_tree=549</TD>
</TR><TR ALIGN='LEFT'>   <TD>waveformview_goto_cursor=1</TD>
   <TD>waveformview_goto_last_time=1</TD>
   <TD>waveformview_goto_time_0=4</TD>
   <TD>xdccategorytree_xdc_category_tree=11</TD>
</TR><TR ALIGN='LEFT'>   <TD>xdcviewertreetablepanel_xdc_viewer_tree_table=5</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addcfgmem=1</TD>
   <TD>addsources=43</TD>
   <TD>autoconnecttarget=2</TD>
   <TD>closeproject=9</TD>
</TR><TR ALIGN='LEFT'>   <TD>closetarget=1</TD>
   <TD>coreview=3</TD>
   <TD>createblockdesign=2</TD>
   <TD>editdelete=34</TD>
</TR><TR ALIGN='LEFT'>   <TD>editproperties=7</TD>
   <TD>editundo=2</TD>
   <TD>exitapp=7</TD>
   <TD>exportioports=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>launchprogramfpga=3</TD>
   <TD>makeactivecnsset=2</TD>
   <TD>movetosimset=1</TD>
   <TD>newhardwaredashboard=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>newproject=4</TD>
   <TD>openhardwaremanager=3</TD>
   <TD>openproject=9</TD>
   <TD>openrecenttarget=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>opentarget=1</TD>
   <TD>refreshdevice=1</TD>
   <TD>reporttiming=1</TD>
   <TD>reporttimingsummary=12</TD>
</TR><TR ALIGN='LEFT'>   <TD>runbitgen=15</TD>
   <TD>runimplementation=31</TD>
   <TD>runschematic=11</TD>
   <TD>runsynthesis=33</TD>
</TR><TR ALIGN='LEFT'>   <TD>savedesign=1</TD>
   <TD>setsourceenabled=2</TD>
   <TD>settargetconstrfile=5</TD>
   <TD>settopnode=17</TD>
</TR><TR ALIGN='LEFT'>   <TD>showbusplot=1</TD>
   <TD>showsource=3</TD>
   <TD>showview=45</TD>
   <TD>simulationbreak=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationrelaunch=1</TD>
   <TD>simulationrestart=59</TD>
   <TD>simulationrun=122</TD>
   <TD>simulationrunall=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationrunfortime=103</TD>
   <TD>timingconstraintswizard=1</TD>
   <TD>toggleviewnavigator=5</TD>
   <TD>toolssettings=18</TD>
</TR><TR ALIGN='LEFT'>   <TD>verifydevice=1</TD>
   <TD>viewlayoutcmd=12</TD>
   <TD>viewtaskimplementation=22</TD>
   <TD>viewtaskprojectmanager=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>viewtaskrtlanalysis=12</TD>
   <TD>viewtasksynthesis=6</TD>
   <TD>waveformsaveconfiguration=2</TD>
   <TD>xdcsetinputdelay=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>zoomfit=7</TD>
   <TD>zoomin=8</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=10</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=2</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=0</TD>
   <TD>export_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=0</TD>
   <TD>export_simulation_questa=0</TD>
   <TD>export_simulation_riviera=0</TD>
   <TD>export_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=0</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=124</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=30</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=1</TD>
   <TD>totalsynthesisruns=1</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=3</TD>
    <TD>carry4=6</TD>
    <TD>fdre=397</TD>
    <TD>fdse=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>gnd=8</TD>
    <TD>ibuf=6</TD>
    <TD>lut1=40</TD>
    <TD>lut2=111</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3=152</TD>
    <TD>lut4=163</TD>
    <TD>lut5=317</TD>
    <TD>lut6=716</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf7=7</TD>
    <TD>muxf8=1</TD>
    <TD>obuf=25</TD>
    <TD>obuft=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36e1=1</TD>
    <TD>vcc=6</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=3</TD>
    <TD>carry4=6</TD>
    <TD>fdre=397</TD>
    <TD>fdse=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>gnd=8</TD>
    <TD>ibuf=79</TD>
    <TD>iobuf=2</TD>
    <TD>lut1=40</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2=111</TD>
    <TD>lut3=152</TD>
    <TD>lut4=163</TD>
    <TD>lut5=317</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6=716</TD>
    <TD>muxf7=7</TD>
    <TD>muxf8=1</TD>
    <TD>obuf=72</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36e1=1</TD>
    <TD>vcc=6</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>phys_opt_design_post_place</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-aggressive_hold_fix=default::[not_specified]</TD>
    <TD>-bram_register_opt=default::[not_specified]</TD>
    <TD>-clock_opt=default::[not_specified]</TD>
    <TD>-critical_cell_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-critical_pin_opt=default::[not_specified]</TD>
    <TD>-directive=default::[not_specified]</TD>
    <TD>-dsp_register_opt=default::[not_specified]</TD>
    <TD>-effort_level=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fanout_opt=default::[not_specified]</TD>
    <TD>-hold_fix=default::[not_specified]</TD>
    <TD>-insert_negative_edge_ffs=default::[not_specified]</TD>
    <TD>-multi_clock_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-placement_opt=default::[not_specified]</TD>
    <TD>-restruct_opt=default::[not_specified]</TD>
    <TD>-retime=default::[not_specified]</TD>
    <TD>-rewire=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-shift_register_opt=default::[not_specified]</TD>
    <TD>-uram_register_opt=default::[not_specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
    <TD>-vhfn=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-cell_types=default::all</TD>
    <TD>-clocks=default::[not_specified]</TD>
    <TD>-exclude_cells=default::[not_specified]</TD>
    <TD>-include_cells=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bram_ports_augmented=0</TD>
    <TD>bram_ports_newly_gated=0</TD>
    <TD>bram_ports_total=2</TD>
    <TD>flow_state=default</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_augmented=0</TD>
    <TD>slice_registers_newly_gated=0</TD>
    <TD>slice_registers_total=398</TD>
    <TD>srls_augmented=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>srls_newly_gated=0</TD>
    <TD>srls_total=0</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>blk_mem_gen_v8_2/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addra_width=10</TD>
    <TD>c_addrb_width=10</TD>
    <TD>c_algorithm=1</TD>
    <TD>c_axi_id_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_slave_type=0</TD>
    <TD>c_axi_type=1</TD>
    <TD>c_byte_size=9</TD>
    <TD>c_common_clk=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_count_18k_bram=0</TD>
    <TD>c_count_36k_bram=1</TD>
    <TD>c_ctrl_ecc_algo=NONE</TD>
    <TD>c_default_data=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_disable_warn_bhv_coll=0</TD>
    <TD>c_disable_warn_bhv_range=0</TD>
    <TD>c_elaboration_dir=./</TD>
    <TD>c_en_deepsleep_pin=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_ecc_pipe=0</TD>
    <TD>c_en_rdaddra_chg=0</TD>
    <TD>c_en_rdaddrb_chg=0</TD>
    <TD>c_en_shutdown_pin=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_sleep_pin=0</TD>
    <TD>c_enable_32bit_address=0</TD>
    <TD>c_est_power_summary=Estimated Power for IP     _     2.4812 mW</TD>
    <TD>c_family=artix7</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_axi_id=0</TD>
    <TD>c_has_ena=0</TD>
    <TD>c_has_enb=0</TD>
    <TD>c_has_injecterr=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_mem_output_regs_a=1</TD>
    <TD>c_has_mem_output_regs_b=0</TD>
    <TD>c_has_mux_output_regs_a=0</TD>
    <TD>c_has_mux_output_regs_b=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_regcea=0</TD>
    <TD>c_has_regceb=0</TD>
    <TD>c_has_rsta=0</TD>
    <TD>c_has_rstb=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_softecc_input_regs_a=0</TD>
    <TD>c_has_softecc_output_regs_b=0</TD>
    <TD>c_init_file=lcd_rom.mem</TD>
    <TD>c_init_file_name=[user-defined]</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_inita_val=0</TD>
    <TD>c_initb_val=0</TD>
    <TD>c_interface_type=0</TD>
    <TD>c_load_init_file=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_mem_type=3</TD>
    <TD>c_mux_pipeline_stages=0</TD>
    <TD>c_prim_type=1</TD>
    <TD>c_read_depth_a=1024</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_read_depth_b=1024</TD>
    <TD>c_read_width_a=24</TD>
    <TD>c_read_width_b=24</TD>
    <TD>c_rst_priority_a=CE</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rst_priority_b=CE</TD>
    <TD>c_rstram_a=0</TD>
    <TD>c_rstram_b=0</TD>
    <TD>c_sim_collision_check=ALL</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_bram_block=0</TD>
    <TD>c_use_byte_wea=0</TD>
    <TD>c_use_byte_web=0</TD>
    <TD>c_use_default_data=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_ecc=0</TD>
    <TD>c_use_softecc=0</TD>
    <TD>c_use_uram=0</TD>
    <TD>c_wea_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_web_width=1</TD>
    <TD>c_write_depth_a=1024</TD>
    <TD>c_write_depth_b=1024</TD>
    <TD>c_write_mode_a=WRITE_FIRST</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_write_mode_b=WRITE_FIRST</TD>
    <TD>c_write_width_a=24</TD>
    <TD>c_write_width_b=24</TD>
    <TD>c_xdevicefamily=artix7</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=6</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=blk_mem_gen</TD>
    <TD>x_ipproduct=Vivado 2015.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=8.2</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_design_analysis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-bounding_boxes=default::[not_specified]</TD>
    <TD>-cells=default::[not_specified]</TD>
    <TD>-complexity=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-congestion=default::[not_specified]</TD>
    <TD>-end_point_clocks=default::[not_specified]</TD>
    <TD>-extend=default::[not_specified]</TD>
    <TD>-extract_metrics=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-file=default::[not_specified]</TD>
    <TD>-full_logical_pin=default::[not_specified]</TD>
    <TD>-hierarchical_depth=default::[not_specified]</TD>
    <TD>-hold=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-logic_level_dist_paths=default::[not_specified]</TD>
    <TD>-logic_level_distribution=default::[not_specified]</TD>
    <TD>-logic_levels=default::[not_specified]</TD>
    <TD>-max_level=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_paths=default::[not_specified]</TD>
    <TD>-min_congestion_level=default::5</TD>
    <TD>-min_level=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_header=default::[not_specified]</TD>
    <TD>-of_timing_paths=default::[not_specified]</TD>
    <TD>-pploc_distance=default::[not_specified]</TD>
    <TD>-qor_summary=[specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-quiet=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-return_timing_paths=default::[not_specified]</TD>
    <TD>-routed_vs_estimated=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-routes=default::[not_specified]</TD>
    <TD>-setup=default::[not_specified]</TD>
    <TD>-show_all_congestion_windows=default::false</TD>
    <TD>-suggestion=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-timing=default::[not_specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>runtime=0.139 secs</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage_count</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>qor_summary=4</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-internal=default::[not_specified]</TD>
    <TD>-internal_only=default::[not_specified]</TD>
    <TD>-max_msgs_per_check=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_waivers=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-ruledecks=default::[not_specified]</TD>
    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufc-1=1</TD>
    <TD>cfgbvs-1=1</TD>
    <TD>rpbf-3=16</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_prohibited=0</TD>
    <TD>bufgctrl_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufgctrl_util_percentage=6.25</TD>
    <TD>bufhce_available=120</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
    <TD>bufio_available=40</TD>
    <TD>bufio_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_prohibited=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
    <TD>bufmrce_available=20</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_prohibited=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=40</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_prohibited=0</TD>
    <TD>bufr_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_util_percentage=0.00</TD>
    <TD>mmcme2_adv_available=10</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_used=0</TD>
    <TD>mmcme2_adv_util_percentage=0.00</TD>
    <TD>plle2_adv_available=10</TD>
    <TD>plle2_adv_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_prohibited=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=740</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_prohibited=0</TD>
    <TD>dsps_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=0</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=365</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_prohibited=0</TD>
    <TD>block_ram_tile_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>block_ram_tile_util_percentage=0.27</TD>
    <TD>ramb18_available=730</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_used=0</TD>
    <TD>ramb18_util_percentage=0.00</TD>
    <TD>ramb36_fifo_available=365</TD>
    <TD>ramb36_fifo_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_prohibited=0</TD>
    <TD>ramb36_fifo_used=1</TD>
    <TD>ramb36_fifo_util_percentage=0.27</TD>
    <TD>ramb36e1_only_used=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=2</TD>
    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=397</TD>
    <TD>fdse_functional_category=Flop &amp; Latch</TD>
    <TD>fdse_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=6</TD>
    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=19</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=112</TD>
    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=154</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=163</TD>
    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=321</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=708</TD>
    <TD>muxf7_functional_category=MuxFx</TD>
    <TD>muxf7_used=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf8_functional_category=MuxFx</TD>
    <TD>muxf8_used=1</TD>
    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=25</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuft_functional_category=IO</TD>
    <TD>obuft_used=2</TD>
    <TD>ramb36e1_functional_category=Block Memory</TD>
    <TD>ramb36e1_used=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=66900</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_prohibited=400</TD>
    <TD>f7_muxes_used=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>f7_muxes_util_percentage=0.01</TD>
    <TD>f8_muxes_available=33450</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_prohibited=200</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_used=1</TD>
    <TD>f8_muxes_util_percentage=&lt;0.01</TD>
    <TD>lut_as_logic_available=133800</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_prohibited=800</TD>
    <TD>lut_as_logic_used=1234</TD>
    <TD>lut_as_logic_util_percentage=0.92</TD>
    <TD>lut_as_memory_available=46200</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_prohibited=0</TD>
    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=269200</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_prohibited=0</TD>
    <TD>register_as_flip_flop_used=398</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_util_percentage=0.15</TD>
    <TD>register_as_latch_available=269200</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
    <TD>slice_luts_available=133800</TD>
    <TD>slice_luts_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_prohibited=800</TD>
    <TD>slice_luts_used=1234</TD>
    <TD>slice_luts_util_percentage=0.92</TD>
    <TD>slice_registers_available=269200</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_prohibited=0</TD>
    <TD>slice_registers_used=398</TD>
    <TD>slice_registers_util_percentage=0.15</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=0</TD>
    <TD>lut_as_logic_available=133800</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_prohibited=800</TD>
    <TD>lut_as_logic_used=1234</TD>
    <TD>lut_as_logic_util_percentage=0.92</TD>
    <TD>lut_as_memory_available=46200</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_prohibited=0</TD>
    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
    <TD>lut_in_front_of_the_register_is_unused_available=0</TD>
    <TD>lut_in_front_of_the_register_is_unused_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_in_front_of_the_register_is_unused_prohibited=0</TD>
    <TD>lut_in_front_of_the_register_is_unused_used=9</TD>
    <TD>lut_in_front_of_the_register_is_used_available=9</TD>
    <TD>lut_in_front_of_the_register_is_used_fixed=9</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_in_front_of_the_register_is_used_prohibited=9</TD>
    <TD>lut_in_front_of_the_register_is_used_used=85</TD>
    <TD>register_driven_from_outside_the_slice_fixed=85</TD>
    <TD>register_driven_from_outside_the_slice_used=94</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_driven_from_within_the_slice_fixed=94</TD>
    <TD>register_driven_from_within_the_slice_used=304</TD>
    <TD>slice_available=33450</TD>
    <TD>slice_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_prohibited=200</TD>
    <TD>slice_registers_available=269200</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_used=398</TD>
    <TD>slice_registers_util_percentage=0.15</TD>
    <TD>slice_used=363</TD>
    <TD>slice_util_percentage=1.09</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=200</TD>
    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=163</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_available=33450</TD>
    <TD>unique_control_sets_fixed=33450</TD>
    <TD>unique_control_sets_prohibited=200</TD>
    <TD>unique_control_sets_used=24</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_util_percentage=0.07</TD>
    <TD>using_o5_and_o6_available=0.07</TD>
    <TD>using_o5_and_o6_fixed=0.07</TD>
    <TD>using_o5_and_o6_prohibited=0.07</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_used=243</TD>
    <TD>using_o5_output_only_available=243</TD>
    <TD>using_o5_output_only_fixed=243</TD>
    <TD>using_o5_output_only_prohibited=243</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_output_only_used=0</TD>
    <TD>using_o6_output_only_available=0</TD>
    <TD>using_o6_output_only_fixed=0</TD>
    <TD>using_o6_output_only_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_used=991</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_prohibited=0</TD>
    <TD>bscane2_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bscane2_util_percentage=0.00</TD>
    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_prohibited=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
    <TD>efuse_usr_available=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_prohibited=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_prohibited=0</TD>
    <TD>frame_ecce2_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_util_percentage=0.00</TD>
    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
    <TD>pcie_2_1_available=1</TD>
    <TD>pcie_2_1_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcie_2_1_prohibited=0</TD>
    <TD>pcie_2_1_used=0</TD>
    <TD>pcie_2_1_util_percentage=0.00</TD>
    <TD>startupe2_available=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_prohibited=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_prohibited=0</TD>
    <TD>xadc_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-debug_log=default::[not_specified]</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
</TR><TR ALIGN='LEFT'>    <TD>-flatten_hierarchy=default::rebuilt</TD>
    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-include_dirs=default::[not_specified]</TD>
    <TD>-incremental=default::[not_specified]</TD>
    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-lint=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
    <TD>-max_uram=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_lc=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-os=default::[not_specified]</TD>
    <TD>-part=xc7a200tfbg676-2</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=ALU_DISPLAY</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:34s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=47.238MB</TD>
    <TD>memory_peak=1182.301MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-sim_mode=default::behavioral</TD>
    <TD>-sim_type=default::</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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